MIPS Processors

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Processor/ MIPS
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MIPS Processors

自从 2014 年发布 MIPS R6 版本之后， MIPS 公司的 IP Core 产品全面转向 MIPS R6 版本，形成覆盖高中低不同性能和应用需求的 Warrior 产品系列， 而把 R6 之前的产品全部归为 Classic 系列。 Warrior 产品系列又分为 M-Class， I-Class 和 P-Class 三个级别，覆盖了从 32 位微控制器到 64 位服务器与基础设施之间的所有领域。

  • P-class 采用 MIPS R6 MIPS 指令集，当前的产品是 P6600 (MIPS64 R6) 和 P5600 (32-bit MIPS32 R5)。
  • I-class 采用 MIPS R6 nanoMIPS 指令集，用于嵌入式设备，当前的产品是 I7200 (2.1 GHz, 32-bit nanoMIPS)，I6500-F (MIPS64 R6)，I6500 (MIPS64 R6) 和 I6400 (MIPS64 R6)。
  • M-class 采用 MIPS R6 microMIPS 指令集，用于微控制器，当前的产品是 M6250 (64 bit，4GB Virtual Memory，750 MHz)，M6200，M51xx。

The MIPS32® and MIPS64® instruction-set architectures, which are seamlessly compatible, allow customers to port from one generation to the next while preserving their investment in existing software.

microMIPS®, a code compression Instruction Set Architecture (ISA) comprised of 16- and 32- bit instructions, that provides similar performance to MIPS32 with a code size reduction of up to 25%.

nanoMIPS designed for embedded devices, it can deliver up to 40% smaller code than MIPS32. With smaller memory accesses and efficient use of the instruction cache, nanoMIPS also helps to reduce system power consumption.

Architecture modules that are encompassed as part of the base architecture include SIMD (Single Instruction Multiple Data operation), Virtualization, Multi-threading (MT) and DSP technologies.

Based on a heritage built over more than three decades of constant innovation, the MIPS architecture is the industry’s most efficient RISC architecture, delivering the best performance and lowest power consumption in a given silicon area.

  • nanoMIPS Architecture
  • MIPS32 Instruction Set Architecture (ISA)
  • MIPS64 Architecture ISA
  • microMIPS ISA
  • MIPS Multi-Threading architecture module
  • MIPS Virtualization architecture module
  • MIPS SIMD architecture module
  • MIPS DSP architecture module
  • MIPS MCU architecture module
  • MIPS16e architecture module

MIPS32 Architecture

The MIPS32 architecture provides seamless upward compatibility to the 64-bit MIPS64® architecture, bringing powerful features, standardized privileged mode instructions, and support for past ISA versions. The MIPS32 architecture incorporates important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing) enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

MIPS64 Architecture

The MIPS64® architecture provides a solid high-performance foundation for future MIPS processor-based development by incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs, and providing a seamless upgrade path from the MIPS32 architecture.

The MIPS32 and MIPS64 architectures incorporate important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing), enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

nanoMIPS Architecture

Designed for embedded devices, nanoMIPS is a variable lengths instruction set architecture (ISA) offering high performance in substantially reduced code size. Under comparable compiler flags, it can deliver up to 40% smaller code than MIPS32. With smaller memory accesses and efficient use of the instruction cache, nanoMIPS also helps to reduce system power consumption.

The nanoMIPS ISA combines recoded and new 16-, 32-, and 48-bit instructions to achieve an ideal balance of performance and code density. It incorporates all MIPS32 instructions and architecture modules including MIPS DSP and MIPS MT, as well as new instructions for advanced code size reduction.

nanoMIPS is supported in release 6 of the MIPS architecture. It is first implemented in the new MIPS I7200 multi-threaded multi-core processor series. Compiler support is included in the MIPS GNU-based development tools.

microMIPS Architecture

Designed for microcontrollers and other small footprint embedded devices, microMIPS is a code compression instruction set architecture (ISA) that offers 32-bit performance with 16-bit code size for most instructions. It maintains 98% of MIPS32 performance while reducing code size by up to 25%, translating to significant silicon cost savings. With smaller memory accesses and efficient use of the instruction cache, microMIPS also helps to reduce system power consumption.

The microMIPS ISA combines recoded and new 16- and 32-bit instructions to achieve an ideal balance of performance and code density. It incorporates all MIPS32 instructions and architecture modules including MIPS DSP and MIPS MT, as well as new instructions for advanced code size reduction. The microMIPS ISA is backward compatible, enabling reuse of optimized MIPS microarchitecture.

microMIPS is supported in releases r3, r5 and r6 of the MIPS architecture. It is implemented in MIPS CPUs including the M14K, microAptiv, and the Warrior M51xx and M62xx series of cores.

MIPS Architecture Modules

MIPS offers a series of architecture modules that allow designers to extend their MIPS32, MIPS64 or microMIPS instruction sets for additional functionality.

MIPS Multi-threading

Hardware multi-threading can make a single processor core appear and function like multiple separate cores for improved performance and efficiency. MIPS delivers this capability in several families of our licensable CPU IP products, providing a differentiated and highly efficient mechanism to achieve higher levels of performance and/or low latency context switching behavior. Find out more about MIPS Multi-threading.

MIPS Virtualization

The MIPS Virtualization (VZ) module provides the foundation for MIPS multi-domain security technology, and enables consolidation of multiple different embedded CPUs into a single core, resulting in lower silicon area and development effort, ultimately decreasing the overall cost and extending battery life.

MIPS SIMD

The MIPS SIMD Architecture (MSA) incorporates a software-programmable solution into the CPU to handle emerging codecs or a small number of functions not covered by dedicated hardware. This programmable solution allows for increased system flexibility. In addition, the MSA is designed to accelerate many compute-intensive applications by enabling generic compiler support.

MIPS DSP

The MIPS DSP module offers licensees a programmable solution for DSP applications, allowing adaptation to changing market needs and extending the life of an SoC design. The DSP module comprises a set of instructions and state in the integer pipeline of MIPS cores and requires minimal additional logic to implement.

MIPS MCU

The MIPS MCU module provides key enhancements for microcontroller applications including enhanced handling of memory-mapped I/O registers and lower interrupt latencies.

MIPS16e

The MIPS16e module is composed of 16-bit compressed code instructions, designed for the embedded processor market and situations with tight memory constraints. The core can execute both 16- and 32-bit instructions intermixed in the same program, and is compatible with both the MIPS32 and MIPS64 Architectures.

Preferred CPU models for Qemu

  • MIPS32R6, mips32r6-generic
  • MIPS64R6, I6400
  • nanoMIPS, I7200
  • MIPS32R2, 34Kf
  • MIPS64R2, MIPS64R2-generic

MIPS-powered SoC

  • 74Kc (2007), Qualcomm Atheros (AR9344 QCA9558), MediaTek (RT3662 RT3883) Broadcom (BCM4706)
  • 1004Kc (2008), MediaTek (MT7621[1004KEc, 880MHz, 32-bit, 2 Gbps routing])
  • 1074Kc (2010), Realtek (RTL8198C)